The present invention relates generally to bipolar transistors having a high emitter efficiency, and more particularly to bipolar transistors with a tunneling barrier in the emitter region.
The emitter efficiency of a bipolar transistor is defined by the fraction of the emitter current that crosses into the collector. It is desirable to design a transistor so that the emitter efficiency is as close to the value one as possible in order to get a large current gain. Optimally, the emitter current should come from majority carrier electrons injected from the emitter to the base, and only a negligible fraction should come from minority carrier holes injected in the opposite direction, since such holes will not contribute to collector current.
The back flow of minority carriers can be minimized by appropriately doping the emitter region more heavily than the base region. Alternatively, the back flow of minority carriers can be minimized by use of an insulating or semi-insulating barrier within the emitter region or at the junction between the emitter and base regions. Majority and minority carriers can pass through Such a barrier in accordance with the phenomenon of quantum mechanical tunneling. Improved emitter efficiency can be achieved by selecting a material for the barrier that exhibits a relatively high barrier height for the minority carriers. Such an arrangement can inhibit the back flow of minority carriers through the barrier and thereby improve the injection efficiency, resulting in optimal current gain for the transistor.
U.S. Pat. No. 4,672,413 describes a barrier emitter transistor that employs the tunneling phenomenon. In one embodiment, a tunneling barrier of silicon dioxide is included between the base and emitter regions. In another embodiment, a tunneling barrier of semi-insulating polycrystalline silicon (SIPOS) is formed within the emitter region.
It has become a standard practice to use silicon dioxide as a barrier material for increasing emitter efficiency by inhibiting the back flow of minority carriers in an NPN transistor. However, silicon dioxide has a relatively wide band gap on the order of 9.0 eV. Therefore, conventional devices use only a thin layer of about nine or ten angstroms of silicon dioxide as the barrier material. A greater thickness would reduce tunneling of both majority and minority carriers through the barrier layer, and thus undesirably increase emitter resistance.
In practice, it has been difficult to consistently produce a silicon dioxide barrier layer of about nine or ten angstroms in thickness. Even with precision processing and equipment, undesirable variations in the barrier oxide thickness occur to a degree that the resulting transistors exhibit relatively large fluctuations in gain from device to device. The present invention overcomes this problem.